Copper metallization of semiconductor interconnects – issues and prospects,” unpublished

The copper electroplating process for dual damascene metallization of semiconductor interconnects is critically reviewed and the breakthroughs that made this process possible are examined. Special emphasis is placed on analyzing the critical issues, barriers, and future prospects for this technology. The parameters that control the deposit thickness distribution on the macroscopic (wafer) scale and on the microscopic (via) scale are compared. Effects due to the resistive seed layer and mass transport limitations, particularly on the micro-scale, are analyzed. Preferred electrolyte compositions, including the effects of plating additives are discussed. Issues pertaining to cell design, scaling and preferred process conditions are considered. Electroplating applications in microelectronics have been traditionally limited, with a few exceptions, to the metallization of printed wiring boards, contacts, and chip carriers, and to the fabrication of magnetic storage devices. Chip level metallization and particularly the extensive interconnect network that carries signals between th